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TDA7571
STPDACsw - Fully digital high efficiency power audio amplifier
Features

Output power 2 x 70W / 1 x 250W @ THD<1% I2S input (FS = 38 to 48kHz) PWM output (FPWM = FS x 8) MCLK input = 256 x FS Operation on 24bit 30V supply voltage (Max.) St-by Mute Stereo/bridge operation selection Protections against short circuit across the load Chip thermal protection External temperature sensor possibility Thermal warning pins Adjustable clip detector pin The maximum output current and voltage swing are depending by the output circuitry (power supply, external power transistors and sensing resistors). The device can work as a stereo single-ended channels or a mono bridge power amplifier.
HiQUAD-64
Description
The TDA7571 i is a fully digital switchmode power audio amplifier with I2S digital input and PWM output. Table 1. Device summary
Order code TDA7571
Package HiQUAD-64
Packing Tray
September 2007
Rev 1
1/21
www.st.com 21
Contents
TDA7571
Contents
1 2 3 Block and simplified application diagram . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 3.2 3.3 3.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Notes on the electrical schematic shown in Figure 3 and 4 . . . . . . . . . . . 13
3.4.1 Main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
Functions, pins and components description . . . . . . . . . . . . . . . . . . . 14
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Short circuit protection current calculation . . . . . . . . . . . . . . . . . . . . . . . . 14 External thermal protection network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Internal thermal protection network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Gate driving network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 External connections description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.8.6 4.8.7 4.8.8 CD, THWEXT, THWINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ST-BY - St-By pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 +Vs-low - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DATA, SEL, SCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 BRIDGE and L/R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.9
Components with critical placement and type . . . . . . . . . . . . . . . . . . . . . 18
5 6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/21
TDA7571
Block and simplified application diagram
1
Figure 1.
Block and simplified application diagram
Block and simplified application diagram
R9 C1 L/R BRIDGE MCLK MASTER CLOCK SD DATA WS WORD SEL SCK CLOCK R10 RFS SGND PGND 46 48 49 50 CHANNEL LEFT HSD+ PROTECTIONS INTERFACE 22 CHANNEL LEFT LSD+ PROTECTIONS 21 23 34 33 R8 C7 Feed Lin 40 28 +Vs-Vref1 9 12 +Vs 42 +Vs-low 13 14 I2S LEFT DIGITAL SIGNAL PROCESSING OSC 10 29 30 31 24 6 15 37 36 38 NTC ST-BY DGND C3 MUTE F 2.5V -2.5V SGND C4 DGND 56 55 REF 39 54 52 32 P/O 41 D1 43 D2 44 t1 45 t2 47 SGND 53 Feed Rin 57 -Vs+Vrefl 25 26,27,58,59 -Vs C5
D01AU1271A
THERMAL PROTECTIONS
5V dig
Spl1 Spl2
+25V R7
18 17 Gpl Gpls Gnls Gnl Snl2 Snl1 +Vs-5 -Vs+5 Spr1 Spr2 Gpr Gprs Gnrs Gpr Snr2 R4 61 60 -Vs+Vrefr Snr1
M4 OUTPUT LOWPASS FILTER M3
35
OUT LEFT
CD SEL1 CD SEL2 CD
R6 -25V
CLIP
5V DIG
THW EXT R1 THW INT C2 NTC
8 7 CHANNEL RIGHT HSD+ PROTECTIONS 4 5 63 RIGHT DIGITAL SIGNAL PROCESSING INTERFACE CHANNEL RIGHT 64 LSD+ 62 PROTECTIONS
+25V R5
M2 OUTPUT LOWPASS FILTER M1
OUT RIGHT
-25V
5V
R2
R3
3/21
Pin description
TDA7571
2
Pin description
Figure 2. Pins connection diagram (top view)
-Vs+Vrefr Feed R in ST-BY MUTE +2.5V Gnrs Snr2 Snr1 sgnd 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 21 22 23 24 25 26 -Vs Gnl Gnls Snl2 Snl1 -Vs+Vrefl 27 28 29 30 31 32 Feed L in CDsel1 CDsel2 CD dgnd -Vs
Gnr
-Vs
64 63 62 61 60 59 N.C. N.C. N.C. Gpr Gprs +Vs-5 Spr2 Spr1 +Vs-Vref1 pgnd N.C. +Vs Spl1 Spl2 -Vs+5 N.C. Gpls Gpl N.C. N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
58 57 56 55 54 53 -2.5V N.C. SCK WS SD t2 MCLK t1 d2 d1 +Vs-low P/O 5Vdig f NTC THWext THWint Rfs L/R bridge
-Vs
AC00242
Table 2.
Pin number 1 2 3 4 5 6 7 8 9 10 11
Pins description
Name N.C. N.C. N.C. Gpr Gprs +Vs-5 Spr2 Spr1 +Vs-Vref1 pgnd N.C. Sensing 2 PMOS, right channel Sensing 1 PMOS, right channel Supply drivers PMOS Power ground Not connected +Vs-12V 0 (ref.) Not connected Not connected Not connected Gate PMOS, right channel Sense gate PMOS, right channel +Vs-12V +Vs-12V +Vs-6 30V 30V 30V 30V 30V Function Voltage limit (low) Voltage limit (high)
4/21
TDA7571 Table 2.
Pin number 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Pin description Pins description (continued)
Name +Vs Spl1 Spl2 -Vs+5 N.C. Gpls Gpl N.C. N.C. Gnl Gnls Snl2 Snl1 -Vs+Vrefl -Vs -Vs Feed L in CDsel1 CD sel2 CD dgnd bridge L/R Rfs THWint THWext NTC f 5Vdig P/O +Vs-low d1 d2 Digital 5V supply output PLL/FREE running osc. option Positive voltage supply low power Dither 1 Dither 2 Not connected Sense gate PMOS, left channel Gate PMOS, left channel Not connected Not connected Gate NMOS, left channel Gate NMOS, left channel Sensing 2 NMOS, left channel Sensing 1 NMOS, left Channel Supply drivers NMOS. left channel Negative power supply Negative power supply Feedback network left channel Clip detector selection 1 Clip detector selection 2 Clip detector output Digital ground Stereo / bridge selection pin 0 = Stereo; 1 = Bridge Bridge Left/Right Selection 1 = Right; 0 = Left pcm-pwm gain conversion resistor Internal thermal warning output External thermal warning output Sensing resistors network 0 (ref) 6V 6V 6V 5.5V 5.5V 5.5V 6V 6V 6V 30 6V 6V -30V -30V -30V -30V -30V -30V -30V -5V 5V 5.5V 5.5V 5.5V -Vs+12V -Vs+12V -Vs+12V +Vs-12V +Vs-12V 30V 30V Function Positive power supply Sensing 1 PMOS, left channel Sensing 2 PMOS, left channel Voltage limit (low) Voltage limit (high) 30V 30V 30V -Vs+6
5/21
Pin description Table 2.
Pin number 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
TDA7571 Pins description (continued)
Name t1 MCLK t2 SD WS SCK N.C. -2.5V sgnd +2.5V MUTE ST-BY Feed R in -Vs -Vs -Vs+Vrefr Snr1 Snr2 Gnrs Gnr I2S serial data I2S word select I2S serial clock Not connected Signal -2.5V supply output Signal ground Signal 2.5V supply output Mute input Stand by input Feedback network right channel Negative voltage supply Negative voltage supply Supply drivers NMOS. Right channel Sensing 2 NMOS, right channel Sensing 1 NMOS, right channel Sense gate NMOS, right channel Gate NMOS, right channel -5 -30V -30V -30V -30V -30V -30V -30V -Vs+12V -Vs+12V -Vs+12V -2.75V 0 (ref) 2.75V 5.5V 6V 5V Master clock input (256 x fs) Function Voltage limit (low) Voltage limit (high) 6V 6V 6V 6V 6V 6V
6/21
TDA7571
Electrical specifications
3
3.1
Electrical specifications
Absolute maximum ratings
Table 3.
Symbol Vs Tj Tstg
Absolute maximum ratings
Parameter Operating supply voltage Junction temperature, operating range Storage temperature, operating range Value 30 -40 to 150 -55 to 150 Unit V C C
3.2
Thermal data
Table 4.
Symbol Rth j-case
Thermal data
Parameter Thermal resistance junction to case Value 3 Unit C/W
3.3
Table 5.
Electrical characteristics
Electrical characteristics (VS = 25V, RL = 4, f = 1kHz, Tj = 25C, FS = 44.1kHz, Single-Ended, application circuit shown in Figure 3, 2 x 65W/1 x 130W system, unless otherwise specified.)
Parameter Operating supply voltage Vst-by = 5V from +VS from +VS-low from -VS from +VS from +VS-low from -VS Test condition Min. 12 25 20 25 0.3 0.2 0.3 250 250 70 250 1.75 Typ. Max. 30 Unit V mA mA mA mA mA mA mV mV W W W
Symbol VS
Iq
Quiescent supply current
Vst-by = 5V Vst-by = 5V Vst-by = 0
Ist-by
Quiescent supply current
Vst-by = 0 Vst-by = 0
Vos Vos Po Po Pd
Output offset voltage Output offset voltage Output power Output power Power dissipation of the TDA7571
Output-GND (single-ended) Output L - Output R (bridge) Single-ended, @ THD = 1% 2 x 70W system Bridge, @ THD = 1% 1 x 250W system @ Pout = 25 W, bridge configuration
7/21
Electrical specifications Table 5.
TDA7571
Electrical characteristics (continued) (VS = 25V, RL = 4, f = 1kHz, Tj = 25C, FS = 44.1kHz, Single-Ended, application circuit shown in Figure 3, 2 x 65W/1 x 130W system, unless otherwise specified.)
Parameter Power dissipation of the external power transistors Total harmonic distortion Test condition @ Pout = 25W, bridge configuration, 1x250W system @ Pout = 10 W, single ended @ Pout = 40 W, bridge Min. Typ. 10 0.1 0.05 10 180 100 85 96 100 110 1.5 0.2 60 2.5 3 3.5 Max. Unit W % % Vrms V dB dB dB dB dB dB V
Symbol Pdt THD
Vohs En
Half scale output voltage Output noise @ IN = -999dBFS
single-ended, output voltage @ IN = -6dBFS "A" weighted, single-ended "A" weighted, bridge "A" weighted, -60dBFS, Singleended PLL option circuit
DR
Dynamic range "A" weighted, -60dBFS, Bridge free running oscillation option
S/N Ge Ge ct Vgspth
Signal-to-noise ratio (noise floor) Gain error Delta gain error between channels Crosstalk Threshold voltage of the Pchannel Vgs sensor (VSpx1 - VGpxs) Threshold voltage of the Pchannel Vgs sensor (VSnxs - VSnx1) Mute attenuation Supply voltage rejection Switching frequency 3.3V Logic inputs low level voltage 3.3V Logic inputs high level voltage 5V Logic inputs low level voltage
"A" weighted, single-ended "A" weighted, bridge f = 1kHz f = 1kHz f = 1kHz, Vo = 1Vrms
Vgsnth Am SVR FSW Vil Vih Vil Vih
2.5 Vo = 1Vrms f = 100Hz, Vr = 0.5V 80 50
3 90 60 FS x 8
3.5
V dB dB KHz
1.5 pin: ST-BY, MUTE, SD, WS, SCK, MCLK bridge 2.3 1.5 3.5
V V V V
pin: L/R, CD SEL1, CD SEL2, P/O, D1, D2. (these pins are typically 5V Logic inputs high level voltage connected to the DGND or 5V dig pins)
8/21
TDA7571 Table 5.
Electrical specifications Electrical characteristics (continued) (VS = 25V, RL = 4, f = 1kHz, Tj = 25C, FS = 44.1kHz, Single-Ended, application circuit shown in Figure 3, 2 x 65W/1 x 130W system, unless otherwise specified.)
Parameter Test condition Min. Typ. Max. Unit
Symbol Clip detector Vcd CDl CDs
Clip detector pin operating voltage (open drain) Clip detector pin leakage current CD off Clip detector pin saturation voltage CD on, 1mA CDsel1=0, CDsel2=0 (near clipping detection)
10 1 1 0.5 1 5 8
V A V % % % %
CDi
Clip detector THD intervention
CDsel1=0, CDsel2=1 CDsel1=1, CDsel2=0 CDsel1=1, CDsel2=1
Protections Thwc Tsdc Tsdch Thws Tsds Tsdsh Vpp Vpn Ispx1 Isnx1 Drivers Vhgp Vlgp Vhgn Vlgn Ihgp High level output voltage (Gpl, Gpr) Low level output voltage (Gpl, Gpr) High level output voltage (Gnl, Gnr) Low level output voltage (Gnl, Gnr) High level output sink current (Gpl, Gpr, peak) +Vs -10 +Vs -Vs -Vs +10 2.2 V V V V A Chip thermal warning intervention Thermal shut-down chip Thermal shut-down chip hysteresis External thermal warning intervention External shut-down intervention External thermal shut-down hysteresis Protection intervention voltage Pchannel (Vspx1-Vspx2) Protection intervention voltage Nchannel (Vsnx2-Vsnx1) Current input pins 7, 13 Current output pins 7, 13 135 145 7 5Vdig x 0.45 5Vdig x 0.37 5Vdig x 0.037 85 85 150 150 150 160 10 5Vdig x 0.48 5Vdig x 0.4 5Vdig x 0.04 100 100 200 200 165 175 13 5Vdig x 0.51 5Vdig x 0.43 5Vdig x 0.043 120 120 260 260 C C C V V V mV mV A A
9/21
Electrical specifications Table 5.
TDA7571
Electrical characteristics (continued) (VS = 25V, RL = 4, f = 1kHz, Tj = 25C, FS = 44.1kHz, Single-Ended, application circuit shown in Figure 3, 2 x 65W/1 x 130W system, unless otherwise specified.)
Parameter Low level output source current (Gpl, Gpr, peak) High level output sink current (Gnl, Gnr, peak) Low level output source current (Gnl, Gnr, peak) Test condition Min. Typ. 2.7 2.5 1.7 Max. Unit A A A
Symbol Ilgp Ihgn Ilgn
Internal power supply 5Vdig 2.5V -2.5V Vref1 5Vdig pin output voltage 2.5V pin output voltage -2.5V pin output voltage Vref1 pin output voltage Reference: dgnd pin Reference: sgnd pin Reference: sgnd pin Reference: + Vs pin Reference: - Vs pin 5 2.5 -2.5 -10 10 V V V V V
Vrefl/Vrefr Vrefl, Vrefr pin output voltage
10/21
TDA7571 Figure 3. PLL option diagram
Electrical specifications
11/21
Electrical specifications Figure 4. Free running oscillator option diagram
TDA7571
12/21
TDA7571
Electrical specifications
3.4
3.4.1
Notes on the electrical schematic shown in Figure 3 and 4
Main characteristics

2 channels single-ended or 1 channel bridge PWM amplifier Power output: see Table 5 Figure 3: PLL option Figure 4: free running oscillator option Output voltage @ input = -6Bfs: - - Figure 3: 10Vrms (single ended) - 20Vrms (bridge) Figure 4: 9.5Vrms (single ended) - 19Vrms (bridge)

Clip detector settled at THD=10% No dithering selected
The schematic is depicted showing the suggested structure of the printed circuit board tracks (star points, high current path, components placement). To avoid malfunctioning due to the parasitic inductance, short connections lengths are recommended. Table 6. Component characteristics
Minimum load: 2 x 4 Ohm single-ended or 8 Ohm bridge (2 x 65W / 1 x 130W) (power supply = 25V) STP12PF06 STP14NF06 Minimum load: 2 x 2 Ohm single-ended or 4Ohm bridge (2 x 125W / 1 x 250W) (power supply = 25V) 2 x STP12PF06 in parallel 2 x STP14NF06 in parallel
Components (See schematic of Figure 3 & 3)
P-MOS-L P-MOS-R N-MOS-L N-MOS-R Rp-N-L2 RP-P-L2 Rp-N-R2 Rp-P-R2
Not present
4.7K
13/21
Functions, pins and components description
TDA7571
4
4.1
Figure 5.
Functions, pins and components description
Short circuit protection current calculation
Short circuit protection current diagram
Imos TDA7571
Rp1 (typ=4.7kOhm)
SPx2 pin
Rsens (not inductive resistor) Typ. Values = 10 - 30 mOhm to -Vs
Cfil (typ 2.2nF) Rfil (typ. 100 Ohm)
Rp2
Vp=100mV Typ comparator SPx1 pin
Vrfil = Ispx1 x Rfil = 20mV Typ
1 - Vpx ( Rp1 + Rp2 ) I lim = ----------------- ------------------------------------------------- + Vfil Rsens Rp2 1I lim = ----------------- ( Vpx + Vfil ) Rsens if Rp2 is not used
4.2
External thermal protection network
The purpose of this function is to sense critical points of the amplifier system, as example the heatsink of the power transistors, avoiding too high temperature. Through the external thermal warning pin (THWEXT, pin 37), a signal useful to reduce the power dissipation reducing (as example) the output power and/or, in a system provided of regulated power supply, reducing the voltage supply of the amplifier (VS) is present. Example of external thermal protection circuitry
Components: - - type: B57621 C621/100k/+ Text = 10K External thermal warning temperature intervention: 90 C External thermal shut down temperature intervention: 100 C External thermal shut down hysteresis: 6C
Results (simulations): - - -
14/21
TDA7571
Functions, pins and components description
4.3
Internal thermal protection network
The purpose of this function is to sense the chip temperature. Because of the power dissipation of this device is almost constant (is not dependent by the output power), the system must be designed to avoid chip temperature higher than 140 C. The internal thermal protection is intended to avoid dangerous situations due to, as example, damaged power transistors (gate-source shorted) or bad environments conditions. Through the internal thermal warning pin (THWINT, pin 36), a signal useful to switch-off the system or, at least, reduce the power dissipation reducing (as example) the output power and/or, in a system provided of regulated power supply, reducing the voltage supply of the amplifier (Vs) is present.
4.4
Feedback
The resistors Rgain-L1, Rgain-L2 for the Left channel and Rgain-R1, Rgain-R2 for the Right channel defines the output AC voltage with a specific input digital data. In the example, with 3.9Kohm and 1kohm, as shown in the schematic, the output voltage @ input = -6dBFS, is indicated in the Main characteristics description. These values are needed to reach the clipping with 0dBFS input digital data and Vs = 25V. If different power supply values are used, different resistors can be used to guarantee the clipping (then the output power), optimizing the signal to noise ratio. If Vsmax is the maximum power supply at which the amplifier must goes into clipping condition, the value of Rgain-X1 is given by: ( V smax R gain - X2 - 5.1 R gain - X2 ) R gain - X1 - --------------------------------------------------------------------------------------------------5.1 Considering Rgain-X2 = 1kohm, the relation become: ( V smax - 5.1 ) R gain - X1 = -----------------------------------5.1 As example, if Vsmax = 20V, Rgain - L1 = Rgain - R1 = 2.92kohm ~= 3kohm
4.5
Gate driving network
The main purpose of the 27 ohm resistors Rd-N-L, Rd-P-L, Rd-N-R and Rd-P-R are the following: 1. 2. Dumping of the L-C equivalent circuit done by the parasitic inductance and capacitance present in the circuit Reduction of the dv/dt of the Vgs and then reduction of the di/dt of the drain current of the power MOS.
The R-C snubber network done by: Rs-N-L, Cs-N-L
15/21
Functions, pins and components description Rs-P-L, Cs-P-L Rs-N-R, Cs-N-R Rs-P-R, Cs-P-R
TDA7571
Are in the direction to increase the dumping (point 1) and reduce the dv/dt (point 2). The value of these components is also depending on the layout structure. With a reduction of the parasitic inductance present in the P.C. board layout, in the region around the power transistors, the value of these components can be reduced, giving advantage in terms of THD, mainly at mid-high power levels, due to the reduction of the "dead zone". The minimum suggested value of Rd-x-x is around 10 Ohm, while, is some cases, Rs-x-x and Cs-x-x can be removed.
4.6
PLL
In case of the schematic shown in Figure 3, the internal oscillator is locked by a PLL circuit at the Master Clock input frequency (MCLK). The loop filter of this PLL is externally connected to the pin F (39). It consists in a lag-lead filter (Cpll1, Rpll). The output resistance of the pin F is a 10K (typ) resistor. The typical suggested values of Cpll1 and Rpll are the following: Cpll1 = 10Kpf Rpll = 1Kohm. In some cases, in a system with few clock interactions and a good MCLK signal, a parallel capacitor Cpll2 of 2.2nF-4.7nF can help to decrease the noise at the pin F. With the PLL option, the A.C. output amplitude is not dependant by the resistor Rosc, because the voltage across Rosc is defined by the PLL itself, Moreover, the output A.C. voltage is independent also from the clock of the PCM signal (32kHz, 44.1kHz, 48kHz). Vice versa, if the free running oscillation is selected, the output signal is dependant by the Rosc value and from the input PCM frequency.
4.7
Dither
With the pins D1 (43) and D2 (44) 4 types of digital dithering is achievable: Table 7. 4 types of digital dithering
D1 1 2 3 4 0 0 1 1 D2 0 1 0 1 Dithering Low Mid-low Mid-high High
Because of the recorded signals (music or speech) already contains some amount of noise, the dithering is generally not needed. For high quality signals, it is suggested do not use the cases 3 and 4, that can be useful only in case of low resolution signals without noise added.
16/21
TDA7571
Functions, pins and components description
4.8
4.8.1
External connections description
CD, THWEXT, THWINT
These pins, if used, it must be connected to a pull-up resistor (>10kOhm) connected to a supply voltage referred to the receiver device (as example, a P). Maximum voltage = 6V.
4.8.2
MUTE
Mute pin
4.8.3
ST-BY - St-By pin.
To avoid pop noise due to multiple ST-BY parasitic pulses, an R-C network must be added (as example 47kOhm, 0.1F)
4.8.4
+Vs-low This pin supply the low voltage circuits. It can be connected to the +Vs or to a reference voltage comprising between 12V to +Vs. A connection to +Vs through a 100Ohm resistor, together a 1uF capacitor placed from +Vslow and GND is possible too.
4.8.5
DATA, SEL, SCK
I2S digital inputs
4.8.6
MCLK
Master clock input. Must be F(MCLK) = 256 x Fs (11289.6kHz in case of Fs = 44.1 kHz)
4.8.7
DGND
Digital ground
4.8.8
BRIDGE and L/R
With this pin, the mode of working of the device (bridge or single-ended) can be selected. If it is connected to the pin 32 (DGND) the device works in single-ended mode If it is connected to the pin 40 (5Vdig) the device works in bridge mode. In case of bridge mode, the pin 34 (L/R) makes the channel selection. If connected to DGND, the Left channel is selected. If connected to 5Vdig, is selected the Right channel. These pins must be selected with the device in ST-BY condition. In case of single-ended operation, it is suggested to put the L/R pin at 5V.
17/21
Functions, pins and components description
TDA7571
4.9
Components with critical placement and type
Ci-L1, Ci-L2, Ci-R1, Ci-R2 must be placed as near as possible to the sources of the respective power MOS. If 2 power MOS in parallel are needed, can be useful to place a couple of capacitors for each couple of power MOS. These capacitors are needed to absorb the high di/dt current present during the Pchannel/Nchannel and Nchannel/Pchannel transition that can cause high peak voltages on the power supply wiring connection due to their parasitic inductance. The capacitors placed between +Vs to GND and to -Vs are distributed along the power lines. With P.C. board with very short connections, some of these capacitors can be avoided (Cvs-1, Cvs-2, Cd3, Cd4, Cd8, Cd7). The current sensing resistors Rsens-N-L, Rsens-P-L, Rsens-P-R and Rsens-N-R must be not inductive components, as example, made by a constant an wire.
18/21
TDA7571
Package information
5
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 6.
DIM. MIN. A A1 A2 A3 b c D D1 (1) D2 E E1 (1) e E2 E3 E4 F G L N S 0.80 2.35 9.30 13.30 9.50 13.50 0.10 0.12 1.10 0.031 10(max.) 0(min.), 7(max.) 0 2.50 0 0.22 0.23 17.00 13.90 2.65 17.00 13.90 14.00 0.65 2.65 9.70 13.70 0.092 0.366 0.523 0.374 0.531 0.004 0.005 0.043 14.00 2.80
HiQUAD-64 mechanical data and package dimensions
mm TYP. MAX. 3.15 0.25 2.90 0.10 0.38 0.32 17.40 14.10 2.95 17.40 14.10 0 0.10 0 0.008 0.009 0.669 0.547 0.104 0.669 0.547 0.551 0.025 0.104 0.382 0.539 0.551 0.110 MIN. inch TYP. MAX. 0.124 0.010 0.114 0.004 0.015 0.012 0.685 0.555 0.116 0.685 0.555
OUTLINE AND MECHANICAL DATA
(1): "D1" and "E1" do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15mm(0.006inch) per side
HiQUAD-64
N
E2 A2 c
A A b
BOTTOM VIEW
33
FM A B
53
e
E3
D2 (slug tail width)
B E1 E E3
slug (bottom side)
Gauge Plane 0.35
C S L A3
SEATING PLANE G C
64 1
21
COPLANARITY
E4 (slug lenght) D1 D
POQU64ME
A1
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Revision history
TDA7571
6
Revision history
Table 8.
Date 3-Sep-2007
Document revision history
Revision 1 Initial release. Changes
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TDA7571
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